Simulation methods and equivalent circuit models for electronic components of this kind are used in circuit simulations in electronic circuit design. The circuit simulations employ circuit simulators, such as a simulation program with integrated circuit emphasis (SPICE). Some circuit simulators can be used at websites of producers of electronic components. A user can access a website of a producer of electronic components from a terminal, such as a personal computer, over the Internet network and use the circuit simulator.
One example of the simulation methods and equivalent circuit models of this type is the one for capacitors disclosed in Japanese Unexamined Patent Application Publication No. 2002-259482.
In this simulation, as illustrated in FIG. 1 in Japanese Unexamined Patent Application Publication No. 2002-259482, given capacitor frequency characteristics of a capacitor are input in a first step, one of an RC circuit, RL circuit, and RCL circuit is formed as an equivalent circuit model representing a circuit enabling simulation in a time domain using frequency-independent resistances (R), capacitances (C), and/or inductances (L) in a second step, an evaluation function for evaluating accuracy of the equivalent circuit model formed in the second step is composed in a third step, and the evaluation function composed in the third step is minimized and thus a circuit constant is determined in a fourth step.
In Japanese Unexamined Patent Application Publication No. 2002-259482, with the above-described configuration, the equivalent circuit model enabling simulation in a time domain for a capacitor with an impedance indicated in a frequency domain is derived, and the electric characteristics of the capacitor in the frequency domain or time domain are estimated by circuit simulation.
One example of known inductor simulation methods and equivalent circuit models is disclosed in Japanese Unexamined Patent Application Publication No. 2010-204869.
As illustrated in FIG. 1(C) in Japanese Unexamined Patent Application Publication No. 2010-204869, this simulation uses an equivalent circuit model in which a series circuit of an inductance L1 and a resistance R1 for skin effect of an internal conductor is connected in parallel to a mutual inductance Lm between a direct-current inductance L0 and the inductance L1 and that parallel circuit is connected in series to the direct-current inductance L0 and a direct-current resistance Rdc1 of the internal conductor. In this equivalent circuit model, an inductance and a resistance of an outer electrode are considered at the same time, the inductance L0 is connected in series to an inductance Ls of the outer electrode, and the direct-current resistance Rdc1 of the inner conductor is connected in series to a direct-current resistance Rdc2 of the outer electrode. A series circuit of a parasitic capacitance Cp of a dielectric constituting a chip in a multilayer chip inductor and a resistance Rp representing a dielectric loss is connected in parallel to the inner sides of the equivalent elements Ls and Rdc2 of the outer electrode.
In Japanese Unexamined Patent Application Publication No. 2010-204869, errors occurring between circuit performance in circuit design and a real one are suppressed by a circuit simulation using the above-described equivalent circuit model.
One example of known capacitor simulation methods and equivalent circuit models is a technique disclosed in Japanese Unexamined Patent Application Publication No. 2012-150579. This technique employs an idealized C circuit model and a wide-band high-precision equivalent circuit model.
As illustrated in FIG. 1(A) in Japanese Unexamined Patent Application Publication No. 2012-150579, the idealized C circuit model is represented by an equivalent circuit including a single capacitive element C as a circuit element. A voltage v applied across the capacitive element C is expressed by the following expression (1).v=vac+Vdc  (1)where vac denotes a time-varying signal voltage and a noise voltage and Vdc denotes DC bias voltage applied across the capacitive element C.
The characteristics in which the capacitive element C is changed by the DC bias voltage Vdc are expressed by the following polynomial expression (2).
                                                        C              =                            ⁢                              C                ⁡                                  (                                      V                                          d                      ⁢                                                                                          ⁢                      c                                                        )                                                                                                        =                            ⁢                                                C                  0                                +                                                      C                    1                                    ⁢                                      V                                          d                      ⁢                                                                                          ⁢                      c                                                                      +                                                      C                    2                                    ⁢                                      V                                          d                      ⁢                                                                                          ⁢                      c                                        2                                                  +                                                      C                    3                                    ⁢                                      V                                          d                      ⁢                                                                                          ⁢                      c                                        3                                                  +                                                      C                    4                                    ⁢                                      V                                          d                      ⁢                                                                                          ⁢                      c                                        4                                                  +                                                      C                    5                                    ⁢                                      V                                          d                      ⁢                                                                                          ⁢                      c                                        5                                                  +                                                                                                      ⁢                                                                    C                    6                                    ⁢                                      V                                          d                      ⁢                                                                                          ⁢                      c                                        6                                                  +                …                                                                        (        2        )            
A current i flowing through the capacitive element C is expressed by the following expression (3).i=C(Vdc)·dv/dt  (3)
To calculate Expression (3), as illustrated in FIG. 1(B) in Japanese Unexamined Patent Application Publication No. 2012-150579, an operation circuit is established. In this operation circuit, the capacitive element C is converted into a nonlinear voltage control voltage source UA3 controlled by the DC bias voltage Vdc. The total voltage v applied across the capacitor passes through low pass filters L1 and R1 each having a significantly low cutoff frequency via a linear voltage control voltage source E1. The DC bias voltage Vdc is thus obtained, and it is provided to the nonlinear voltage control voltage source UA3. The total voltage v is supplied to the input terminal of a differentiator UA1 via a linear voltage control voltage source E2, and thus differentiation dv/dt is performed. An output voltage v1 of the differentiator UA1 is input into a three-terminal multiplier UA2, together with an output voltage (C(Vdc)) of the nonlinear voltage control voltage source UA3, which is a substitute for the capacitive element C, and thus multiplication (C(Vdc)·dv/dt) is performed. In this manner, a result of the multiplication is output to an output terminal of the multiplier UA2. Because an output voltage v2 of the multiplier UA2 is equal to the product of the current i flowing through the capacitor and a unit resistance, it is replaced with the capacitor using a linear voltage control current source G controlled by the output voltage v2.
Such an idealized C circuit model is not suited for circuit simulation because a difference from the impedance characteristics of an actual component, in particular, difference in a high-frequency band is too large, but it is useful for an early stage in circuit design or prediction of circuit characteristics.
The wide-band high-precision equivalent circuit model disclosed in Japanese Unexamined Patent Application Publication No. 2012-150579 is applied to a simulation of a multilayer ceramic capacitor (MLCC). This simulation uses the equivalent circuit model having the circuit configuration illustrated in FIG. 5(A) in Japanese Unexamined Patent Application Publication No. 2012-150579. As illustrated in FIG. 5(B) in Japanese Unexamined Patent Application Publication No. 2012-150579, in a multilayer chip capacitor 10, a plurality of internal electrodes are stacked, and electrodes are extended out therefrom in opposite directions in an alternating manner. The equivalent circuit illustrated in FIG. 5(A) in Japanese Unexamined Patent Application Publication No. 2012-150579 takes the thickness of each of the plurality of internal electrodes 20 of the multilayer chip capacitor 10 into consideration. In addition to the electromagnetic effect in an upper surface 22 and a lower surface 24 in each of the plurality of internal electrodes 20, the electromagnetic effect in a first side surface 26 and a second side surface 28 and an open end surface 30 of the plurality of internal electrodes 20 are considered.
All values of various circuit elements in this equivalent circuit are changed by a DC bias voltage. The changes in characteristics of each of the circuit elements caused by the DC bias voltage are expressed by a polynomial expression, and the equivalent circuit model of the MLCC when these changes in characteristics are considered is illustrated in FIG. 12. This model employs a differentiator, multiplier, three-terminal and four-terminal adders and also uses a divider and five-terminal adder. Such a wide-band high-precision model that considers the changes in characteristics caused by the DC bias voltage can achieve good simulation precision in a wide frequency band.